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Specifications ISPGAL22V10
ISPGAL22V10
In-System Programmable E2CMOS PLD Generic Array LogicTM
FEATURES * IN-SYSTEM PROGRAMMABLETM (5-V ONLY) -- 4-Wire Serial Programming Interface -- Minimum 10,000 Program/Erase Cycles -- Built-in Pull-Down on SDI Pin Eliminates Discrete Resistor on Board (ISPGAL22V10C Only) * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- 7.5 ns Maximum Propagation Delay -- Fmax = 111 MHz -- 5 ns Maximum from Clock Input to Data Output -- UltraMOS(R) Advanced CMOS Technology * ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS * COMPATIBLE WITH STANDARD 22V10 DEVICES -- Fully Function/Fuse-Map/Parametric Compatible with Bipolar and CMOS 22V10 Devices * E2 CELL TECHNOLOGY -- In-System Programmable Logic -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention * TEN OUTPUT LOGIC MACROCELLS -- Maximum Flexibility for Complex Logic Designs * APPLICATIONS INCLUDE: -- DMA Control -- State Machine Control -- High Speed Graphics Processing -- Software-Driven Hardware Configuration * ELECTRONIC SIGNATURE FOR IDENTIFICATION DESCRIPTION PIN CONFIGURATION The ISPGAL22V10, at 7.5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the industry's first in-system programmable 22V10 device. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The ISPGAL22V10 is fully function/fuse map/parametric compatible with standard bipolar and CMOS 22V10 devices. The standard PLCC package provides the same functional pinout as the standard 22V10 PLCC package with No-Connect pins being used for the ISP interface signals. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified.
I I I MODE I I I 11 12 14 16 18 19 7 5
FUNCTIONAL BLOCK DIAGRAM
RESET
I/CLK
8 OLMC
I/O/Q
I
10
I
12
OLMC
I/O/Q
I
OLMC
I/O/Q
PROGRAMMABLE AND-ARRAY (132X44)
I
14 OLMC
I/O/Q
I
16 OLMC
I/O/Q
I
16 OLMC
I/O/Q
I
14 OLMC
I
I/O/Q
12
I
OLMC
I/O/Q
I
10 OLMC
I/O/Q
I SDO SDI MODE SCLK
PROGRAMMING LOGIC
8 OLMC
I/O/Q
PRESET
PLCC
I/CLK SCLK I/O/Q I/O/Q I I Vcc
SSOP
4
2
28
26
25 I/O/Q I/O/Q
SCLK I/CLK I I I I I MODE I I I I I GND 1 28 Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q SDO I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I SDI
ISPGAL22V10
Top View
23
I/O/Q SDO
7
ispGAL 22V10 22
Top View
9
21
I/O/Q I/O/Q I/O/Q
14
15
I
I
GND
SDI
I
Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
I/O/Q
I/O/Q
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
isp22v10_02
1
Specifications ISPGAL22V10
ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns) 7.5 Tsu (ns) 6.5 Tco (ns) 5 Icc (mA) 140 Ordering # ISPGAL22V10C-7LJ ISPGAL22V10C-7LK ISPGAL22V10B-7LJ 10 7 7 140 ISPGAL22V10C-10LJ ISPGAL22V10C-10LK ISPGAL22V10B-10LJ 15 10 8 140 ISPGAL22V10C-15LJ ISPGAL22V10C-15LK ISPGAL22V10B-15LJ Package 28-Lead PLCC 28-Lead SSOP 28-Lead PLCC 28-Lead PLCC 28-Lead SSOP 28-Lead PLCC 28-Lead PLCC 28-Lead SSOP 28-Lead PLCC
Industrial Grade Specifications
Tpd (ns) 15 Tsu (ns) 10 Tco (ns) 8 Icc (mA) 165 Ordering # ISPGAL22V10C-15LJI ISPGAL22V10C-15LKI Package 28-Lead PLCC 28-Lead SSOP
PART NUMBER DESCRIPTION
XXXXXXXX _ XX X XX
ISPGAL22V10C Device Name ISPGAL22V10B Speed (ns) L = Low Power Power Grade Blank = Commercial I = Industrial
Package J = PLCC K = SSOP
2
Specifications ISPGAL22V10
OUTPUT LOGIC MACROCELL (OLMC)
The ISPGAL22V10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two OLMCs have sixteen product terms (pins 21 and 23). In addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. The ISPGAL22V10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen.
AR
D Q CLK SP Q
4 TO 1 MUX
2 TO 1 MUX
ISPGAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
Each of the Macrocells of the ISPGAL22V10 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC's D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop's /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either "on" (dedicated output), "off" (dedicated input), or "productterm driven" (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array.
3
Specifications ISPGAL22V10
REGISTERED MODE
AR
AR
D
Q
D
Q
CLK SP
Q
CLK SP
Q
ACTIVE LOW S0 = 0 S1 = 0 S0 = 1 S1 = 0
ACTIVE HIGH
COMBINATORIAL MODE
ACTIVE LOW S0 = 0 S1 = 1 S0 = 1 S1 = 1
ACTIVE HIGH
4
Specifications ISPGAL22V10
ISPGAL22V10 LOGIC DIAGRAM / JEDEC FUSE MAP
PLCC & SSOP Package Pinout
2
0
0000 0044 . . . 0396
4
8
12
16
20
24
28
32
36
40
ASYNCHRONOUS RESET (TO ALL REGISTERS)
8
OLMC
S0 5808 S1 5809
27
0440 . . . . 0880
10
OLMC
S0 5810 S1 5811
26
3
0924 . . . . . 1452
12
OLMC
S0 5812 S1 5813
25
4
1496 . . . . . . 2112
14
OLMC
S0 5814 S1 5815
24
5
2156 . . . . . . . 2860
16
OLMC
S0 5816 S1 5817
23
6
2904 . . . . . . . 3608
16
OLMC
S0 5818 S1 5819
21
7
3652 . . . . . . 4268
14
OLMC
S0 5820 S1 5821
20
9
4312 . . . . . 4840
12
OLMC
S0 5822 S1 5823
19
10
4884 . . . . 5324
10
OLMC
S0 5824 S1 5825
18
11
5368 . . . 5720
8
OLMC
S0 5826 S1 5827
17
12
5764
13
5828, 5829 ...
M S B L S B
SYNCHRONOUS PRESET (TO ALL REGISTERS)
16
Electronic Signature
... 5890, 5891
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
5
Specifications ISPGAL22V10C Specifications ISPGAL22V10 ISPGAL22V10B
ABSOLUTE MAXIMUM RATINGS(1)
Supply voltage VCC ....................................... -0.5 to +7V Input voltage applied ........................... -2.5 to VCC +1.0V Off-state output voltage applied........... -2.5 to VCC +1.0V Storage Temperature.................................. -65 to 150C Ambient Temperature with Power Applied ......................................... -55 to 125C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
RECOMMENDED OPERATING COND.
Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V Industrial Devices: Ambient Temperature (TA) ............................ -40 to 85C Supply voltage (VCC) with Respect to Ground ..................... +4.50 to +5.50V
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current1 SDI Low Leakage Current
2
CONDITION
MIN.
Vss - 0.5
TYP.4 -- -- -- -- -- -- -- -- -- -- --
MAX. 0.8 Vcc+1 -100 250 10 1 0.5 -- 16 -3.2 -130
UNITS V V A A A mA V V mA mA mA
VIL VIH IIL IIH VOL VOH IOL IOH IOS3
2.0 0V VIN VIL (MAX.) 0V VIN VIL (MAX.) 3.5V VIN VCC VIN = VOH (MIN.) IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH -- -- -- -- -- 2.4 -- -- VCC = 5V VOUT = 0.5V TA = 25C -30
Input or I/O High Leakage Current SDI High Leakage Current2 Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current
COMMERCIAL ICC Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open
L -7/-10/-15
--
90
140
mA
INDUSTRIAL ICC Operating Power
Supply Current
VIL = 0.5V
VIH = 3.0V
L -15
--
90
165
mA
ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up on all pins (except SDI on ISPGAL22V10C). See Input Buffer section for more information. 2) The leakage current is due to the internal pull-down on the SDI pin (ISPGAL22V10C only). See Input Buffer section for more information. 3) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 4) Typical values are at Vcc = 5V and TA = 25 C
6
Specifications ISPGAL22V10C Specifications ISPGAL22V10 ISPGAL22V10B
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
COM PARAMETER COM COM/IND
TEST COND.1 A A -- -- -- -- A
DESCRIPTION Input or I/O to Combinatorial Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Feedback before Clock Setup Time, SP before Clock Hold Time, Input or Feedback after Clock Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled Input or I/O to Output Disabled Input or I/O to Asynchronous Reset of Register Asynchronous Reset Pulse Duration Asynchronous Reset to Clock Recovery Time Synchronous Preset to Clock Recovery Time -- -- -- 6.5 10 0 87
-7 MIN. MAX. 7.5 5 2.5 -- -- -- --
-10 MIN. MAX. -- -- -- 7 10 0 71.4 -- -- -- 10 7 2.5
-15 MIN. MAX. -- -- -- 10 10 0 55.5 15 8 2.5 -- -- -- -- UNITS ns ns ns ns ns ns MHz
tpd tco tcf2 tsu1 tsu2 th
fmax3
A A
111 111
-- --
105 105
-- --
80 83.3
-- --
MHz MHz
twh twl ten tdis tar tarw tarr tspr
-- -- B C A -- -- --
4 4 -- -- -- 8 8 10
-- -- 8 8 13 -- -- --
4 4 -- -- -- 8 8 10
-- -- 10 10 13 -- -- --
6 6 -- -- -- 15 10 10
-- -- 15 15 20 -- -- --
ns ns ns ns ns ns ns ns
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section.
CAPACITANCE (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 8 8 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
7
Specifications ISPGAL22V10
SWITCHING WAVEFORMS
INPUT or I/O FEEDBACK
VALID INPUT
INPUT or I/O FEEDBACK
VALID INPUT
tpd
COMBINATORIAL OUTPUT
ts u
CLK
th
tc o
Combinatorial Output
REGISTERED OUTPUT
1/
fm a x
(external fdbk)
Registered Output
INPUT or I/O FEEDBACK
tdis
OUTPUT
ten
CLK
1/
fm a x
(int ern al fd bk )
Input or I/O to Output Enable/Disable
REGISTERED FEEDBACK
tc f
tsu
tw h
CLK
1/
tw l
fmax with Feedback
fm a x
(w/o fdbk)
Clock Width
INPUT or I/O FEEDBACK DRIVING SP CLK
INPUT or I/O FEEDBACK DRIVING AR
tsu
th
tspr
CLK
tarw
tco
REGISTERED OUTPUT
REGISTERED OUTPUT
tarr
tar
Synchronous Preset Asynchronous Reset
8
Specifications ISPGAL22V10
fmax DESCRIPTIONS
CL K
CLK
LOGIC ARR AY
R EG I S T E R
LOGIC ARRAY
REGISTER
ts u
tc o
tcf tpd
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
CLK
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
LOGIC ARRAY
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/twh + twl. This is to allow for a clock duty cycle of other than 50%.
SWITCHING TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 3ns 10% - 90% 1.5V 1.5V See Figure
FROM OUTPUT (O/Q) UNDER TEST TEST POINT R1 +5V
3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition A B C Active High Active Low Active High Active Low R1 300 300 300 R2 390 390 390 390 390 CL 50pF 50pF 50pF 5pF 5pF
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
9
Specifications ISPGAL22V10
ELECTRONIC SIGNATURE
An electronic signature (ES) is provided in every ISPGAL22V10 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. The electronic signature is an additional feature not present in other manufacturers' 22V10 devices. To use the extra feature of the user-programmable electronic signature it is necessary to choose a Lattice Semiconductor 22V10 device type when compiling a set of logic equations. In addition, many device programmers have two separate selections for the device, typically an ISPGAL22V10 and a ISPGAL22V10-UES (UES = User Electronic Signature) or ISPGAL22V10-ES. This allows users to maintain compatibility with existing 22V10 designs, while still having the option to use the GAL device's extra feature. The JEDEC map for the ISPGAL22V10 contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. However, the ISPGAL22V10 device can still be programmed with a standard 22V10 JEDEC map (5828 fuses) with any qualified device programmer. shifting data into the device. Once the function is programmed, the non-volatile E2CMOS cells will not lose the pattern even when the power is turned off. All necessary programming is done via four TTL level logic interface signals. These four signals are fed into the on-chip programming circuitry where a state machine controls the programming. The interface signals are Serial Data In (SDI), Serial Data Out (SDO), Serial Clock (SCLK) and Mode (MODE) control. For details on the operation of the internal state machine and programming of ISPGAL22V10 devices please refer to the ISP Architecture and Programming section in this Data Book.
OUTPUT REGISTER PRELOAD
When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brownouts, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The ISPGAL22V10 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically.
SECURITY CELL
A security cell is provided in every ISPGAL22V10 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by reprogramming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.
INPUT BUFFERS
ISPGAL22V10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. All input and I/O pins (except SDI on the ISPGAL22V10C) also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). The SDI pin on the ISPGAL22V10C has a built-in pull-down to keep the device out of the programming state if the pin is not actively driven. However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. (See equivalent input and I/O schematics on the following page.) Typical Input Current
0
LATCH-UP PROTECTION
ISPGAL22V10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with nchannel pullups instead of the traditional p-channel pullups to eliminate any possibility of SCR induced latching.
DEVICE PROGRAMMING
The ISPGAL22V10 device uses a standard 22V10 JEDEC fusemap file to describe the device programming information. Any third party logic compiler can produce the JEDEC file for this device.
Input Current (A)
IN-SYSTEM PROGRAMMABILITY
The ISPGAL22V10 device features In-System Programmable technology. By integrating all the high voltage programming circuitry on-chip, programming can be accomplished by simply
-20
-40 -60 0 1.0 2.0 3.0 4.0 5.0
Input Voltage (Volts)
10
Specifications ISPGAL22V10
POWER-UP RESET
Vcc Vcc (min.)
tsu
CLK
twl tpr
INTERNAL REGISTER Q - OUTPUT
Internal Register Reset to Logic "0"
ACTIVE LOW OUTPUT REGISTER
Device Pin Reset to Logic "1"
ACTIVE HIGH OUTPUT REGISTER
Device Pin Reset to Logic "0"
Circuitry within the ISPGAL22V10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the
asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the ISPGAL22V10. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN
PIN
Feedback
(Vref Typical = 3.2V)
Active Pull-up Circuit (Except SDI on ISPGAL22V10C)
Vcc
Active Pull-up Circuit Tri-State Control Vcc Vref
(Vref Typical = 3.2V)
Vcc
ESD Protection Circuit
Vref
Vcc
PIN
Data Output ESD Protection Circuit
PIN
Pull-down Resistor (SDI on ISPGAL22V10C Only)
Feedback (To Input Buffer)
Input
Output
11
Specifications ISPGAL22V10
ISPGAL22V10C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tco vs Vcc
1.2
Normalized Tsu vs Vcc
Normalized Tpd
1.1
Normalized Tco
Normalized Tsu
1.1
1.1
1
1
1
0.9
0.9
0.9
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.3 1.3
Normalized Tco vs Temp
1.4
Normalized Tsu vs Temp
Normalized Tpd
Normalized Tco
Normalized Tsu
-55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7 -55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7
1.3 1.2 1.1 1 0.9 0.8 0.7 -55 -25 0 25 50 75 100 125
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching Delta Tco vs # of Outputs Switching
0
Temperature (deg. C)
0
Delta Tpd (ns)
-0.25
Delta Tco (ns)
1 2 3 4 5 6 7 8 9 10
-0.25
-0.5
-0.5
-0.75
-0.75
-1
-1 1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
10 8
Delta Tco vs Output Loading
12
Delta Tco (ns)
Delta Tpd(ns)
RISE FALL
10 8 6 4 2 0 -2
RISE FALL
6 4 2 0 -2 0 50
100
150
200
250
300
0
50
100
150
200
250
300
Ouput Loading (pF)
Output Loading (pF)
12
Specifications ISPGAL22V10
ISPGAL22V10C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
3 2.5 5 4
Voh vs Ioh
4.5
Voh vs Ioh
4.25
Voh (V)
3 2 1 0
1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00
Voh (V)
10.00 20.00 30.00 40.00 50.00 60.00
Vol (V)
2
4
3.75
3.5 0.00 1.00 2.00 3.00 4.00
0.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.2 1.3
Normalized Icc vs Temp
1.20
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
1.1
Normalized Icc
-55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7
1.10
1
1.00
0.9
0.90
0.8 4.50 4.75 5.00 5.25 5.50
0.80 0 25 50 75 100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vcc
5 0 10 20 30 3 2 1 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Delta Icc (mA)
4
Iik (mA)
40 50 60 70 80 90 100 -2.00 -1.50 -1.00 -0.50 0.00
Vin (V)
Vik (V)
13
Specifications ISPGAL22V10 Notes
14

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